ESD protection is an important consideration in integrated circuit design, particularly, as semiconductor structure and component dimensions are scaled down to deep submicron (i.e., less than 0.65 .mu.m) resolutions. During an ESD event, charge is transferred at a high voltage to a pin of an integrated circuit chip during a short duration, i.e., typically less than 1 .mu.sec. Most semiconductor integrated circuits include MOS devices such as MOSFETs with very thin gate oxides or lightly doped drains and sources which are highly susceptible to damage during ESD events. As such devices are made smaller, they can be damaged by even lower voltage ESD events.
FIG. 1 depicts a schematic of an ESD protection circuit 10 of an integrated circuit. Circuits 16 and 18 provide ESD protection to input buffer 12 from ESD voltages which may be applied to the input pad 14. When an ESD event occurs, the diodes of the circuit 16 shunt most of the ESD charge. When the polarity of the ESD voltage is negative, diode D1 shunts ESD charge to the V.sub.SS bus and when the polarity of the ESD voltage is positive, diode D2 shunts ESD charge to the V.sub.DD bus. The circuit 18 includes a resistor R connected in series with a grounded FET clamp M0. The circuit 18 limits the voltage which is applied across the gates of the input buffer 12. The core clamp 20 provides ESD protection to the V.sub.DD and V.sub.SS power busses by transferring ESD charge between the V.sub.DD and V.sub.SS power busses during an ESD event.
Most ESD protection devices are designed to be triggered when a high ESD voltage is applied between two pins of an integrated circuit chip. However, recent attention has been directed to protecting against ESD voltages which may be applied across power busses of the integrated circuit chip. See C. Duvvury, R. Rountree & O. Adams, Internal Chip ESD Protection Beyond the Protection Circuit, I.E.E.E TRANS. OF ELEC. DEVS., vol. 35, no. 12, p. 2133-38, Dec., 1988; J. LeBlanc & M. Chaine, Proximity Effects of "unused" Output Buffers on ESD Performance, I.E.E.E. IRPS PROC., p. 327-30 (1991). These references note that the ESD protection circuits provided between the V.sub.DD and V.sub.SS pins may not provide sufficient protection to the internal devices of the chip. Rather, the chip may, by virtue of the layout of the regions and structures of the internal devices, incorporate parasitic bipolar junction devices which turn-on in advance of the triggering of the ESD protection circuits resulting in damage to the internal devices.
Consider, for example, the circuits depicted in FIGS. 2-4. FIG. 2 depicts the schematic of two closely placed internal circuits. In particular, a first circuit 22 includes an NMOS transistor N1 which is placed laterally adjacent to an NMOS transistor N2 of a second circuit 24. An overhead view of this configuration is shown in FIG. 3 and a cross-section of this configuration, taken at the line X-X', is shown in FIG. 4. The transistor N1 has a gate 30, a source 36 and a drain 38. The source 36 and drain 38 are N.sup.+ regions which extend from the surface of a substrate 34. The transistor N2 has a gate 30', a source 40 and a drain 42. Like the transistor N1, the source 40 and drain 42 are N.sup.+ regions which extend from the surface of the substrate 34.
The drain 38 of transistor N1 is connected to the V.sub.DD power bus line 32 by contacts 28 and the source 40 of the transistor N2 is connected to the V.sub.SS power bus line 32' by contacts 28'.
As shown in FIG. 4, the drain 38 is adjacent, and in close proximity, to the source 40. The N.sup.+ drain region 38, N+ source region 40 and P-conductivity type bulk substrate 34 between the source 40 and drain 38 form an NPN parasitic bipolar junction device 44. During an ESD event, an ESD voltage may be applied between the V.sub.DD power bus line 32 and the V.sub.SS power bus line 32'. Because of the proximity of the N' drain 38 and source 40 region, the requisite turn-on voltage of the parasitic BJT (bipolar junction transistor) 44 can be as low as 13 volts. The ESD voltage between the V.sub.DD and V.sub.SS power bus lines 32 and 32' may be sufficiently high to turn on the parasitic BJT 44 and cause it to operate in "snap-back" mode. This can result in the flow of a large current which can damage the components and structures of the integrated circuit. Note the BJT 44 can turn on at a lower voltage than the circuit which provides ESD protection for ESD events that occur on the power busses (e.g., the core clamp circuit 20 of FIG. 1) and thereby cause damage during an ESD event despite the provision of such ESD protection circuitry.
The prior art has suggested to avoid such internal damage owing to parasitic bipolar junction devices by increasing the spacing between various components and structures (e.g., between the drain 38 and the source 40 of the transistors N1 and N2) by 20 .mu.m. However, this wastes a large amount of precious space on the integrated circuit chip thereby reducing the density of structures and components on each integrated circuit chip. Furthermore, this does not completely prevent the parasitic bipolar junction device from damaging the integrated circuit.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.